Analytical synthesis method and otra-based circuit structure

ABSTRACT

An analytical synthesis method (ASM) for designing a higher-order voltage-mode operational trans-resistance amplifier and capacitor (OTRA-C) based filter is disclosed. A decomposition of a complicated nth-order transferring a function is converted into a set of equations corresponding to a set of sub-circuitries. Then, a circuit structure is constructed by combining said sub-circuitries.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention generally relates to filter design, and more particularly to an OTRA-based circuit.

2. Description of Related Art

An operational trans-resistance amplifier (OTRA), having the dual input-and-output characteristics of the well-known operational transconductance amplifier (OTA), becomes one of the most prospective active elements in the field of analog circuit design. The operational trans-resistance amplifier (OTRA) has the following input-and-output relationships: (i) the two + and − terminal input voltages, V+=V−=0, (ii) the output voltage, Vo=(I+−I−)Rm in which Rm is the trans-resistance of an OTRA, and I+ and I− are the two + and − terminal input currents, (iii) very low input impedance, and (iv) very low output impedance. Based upon the above two sets of input-and-output characteristics, it is apparent that an OTRA is the dual of an OTA and vice versa. In addition to this, the main advantage of eliminating the parasitics at the input port of an OTRA due to virtually grounded input terminals is an extra benefit and very attractive for designers.

Hence, several distinct OTRAs have been proposed in the literature since 1992. So do many different kinds of analog circuits, such as integrators, immittance simulators, oscillators, square/triangular waveform generators, monostable and bistable multivibrators, first-order and second-order all-pass filters, and other second-order single-function and multi-function and high-order filters. A universal biquad filter using four (two more) capacitors was presented. However, none of the elliptic Cauer filters using OTRAs has been presented. Elliptic Cauer filter is a better choice than other kinds of filters for meeting the stringent cut-off rate of a very narrow transition band, under the restriction of a finite order.

SUMMARY OF THE INVENTION

In view of the foregoing, an embodiment of the present invention provides an analytical synthesis method (ASM) for designing a better filter with fewer OTRAs and capacitors.

According to an embodiment of the present invention, a decomposition of a complicated nth-order transferring a function is converted into a set of equations corresponding to a set of sub-circuitries. Then, a circuit structure is constructed by combining said sub-circuitries. That is, an nth-order transfer function is manipulated and decomposed by a succession of innovative algebra operations until a set of simple equations are produced.

The above and other aspects of the invention will become better understood with regard to the following detailed description of the preferred but non-limiting embodiment(s). The following description is made with reference to the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A-1B show two different realizations for the kth OTRA based sub-circuitries, and k=2, 4, . . . , n−1 and n is an odd number, according to an embodiment of the invention;

FIGS. 2A-2B show two different realizations for the n+1th OTRA based sub-circuitries according to the embodiment of the invention;

FIGS. 3A-3B show two different Elliptic OTRA-C based odd-nth-order high-pass Cauer Filter structures according to the embodiment of the invention;

FIGS. 4A-4B show two different realizations for the elliptic OTRA-C based third-order high-pass Cauer filter according to the embodiment of the invention;

FIGS. 5A-5B show two different realizations for the kth OTRA based sub-circuitries, and k=2, 4, . . . , n−1 and n is an odd number, according to another embodiment of the invention;

FIGS. 6A-6B show two different realizations for the nth OTRA based sub-circuitries according to another embodiment of the invention;

FIGS. 7A-7B show two Elliptic OTRA-C based odd-nth-order high-pass Cauer Filter structures according to another embodiment of the invention:

FIGS. 8A-8B show two Elliptic OTRA-C based third-order high-pass Cauer filters;

FIG. 9 shows an Elliptic OTRA-C based odd-nth-order Cauer Filter structure according to one embodiment of the invention;

FIG. 10 shows a realization for the elliptic OTRA-C based third-order Cauer filter according to the embodiment of the invention;

FIG. 11 shows an Elliptic OTRA-C based even-nth-order Cauer Filter structure according to one embodiment of the invention;

FIG. 12 shows a realization for the elliptic OTRA-C based fourth-order Cauer filter according to the embodiment of the invention;

FIG. 13 shows an Elliptic OTRA-C based even-nth-order Cauer Filter structure according to one embodiment of the invention;

FIG. 14 shows a realization for the elliptic OTRA-C based fourth-order Cauer filter according to the embodiment of the invention; and

FIG. 15 shows a Non-linearity cancellation in two matched-NMOS transistor circuit.

DETAILED DESCRIPTION OF THE INVENTION

Novel OTRA-C elliptic Cauer filters using new analytical synthesis methods are disclosed. A decomposition of a complicated nth-order transferring a function is converted into a set of equations corresponding to a set of sub-circuitries. Then, a circuit structure is constructed by combining said sub-circuitries. Since Rm→∞ is used as the design rule, which is not a reality, this results in a better filter with fewer OTRAs. Since more precise component values lead to worse output accuracy, better output precision may result from less accurate component values. Component sensitivity tendency and variation quantity is referred to select one or two proper capacitor(s)/resistance(s) by an appropriate variation to achieve more precise responses. The following specification applies OTRA-C elliptic Cauer filters as examples to illustrate the present invention.

New analytical synthesis methods (ASMs), shown as follows, will be presented for the realizations of the present invention. The synthesis concept is based upon the main input-and-output characteristic of an OTRA: Vo=(I+−I−)Rm. Since the trans-resistance Rm is very large, it is supposed to approach infinity, i.e., Rm→∞. Thus, I+ must equal I−. This rule is using to do the synthesis.

Embodiment 1

The transfer function of a conventional elliptic voltage-mode odd-nth-order Cauer filter which produces only low-pass signals is given by

$\begin{matrix} {\frac{V_{out}}{V_{in}} = \frac{{b_{n - 1}s^{n - 1}} + {b_{n - 3}s^{n - 3}} + \ldots + {b_{2}s^{2}} + b_{0}}{{a_{n}s^{n}} + {a_{n - 1}s^{n - 1}} + {a_{n - 2}s^{n - 2}} + {\ldots \mspace{14mu} a_{2}s^{2}} + {a_{1}s} + a_{0}}} & (1) \end{matrix}$

where n is an odd integer. As the s in equation (1) is replaced by 1/s, the resulting is shown in equation (2) which is the transfer function of an elliptic voltage-mode odd-nth-order high-pass Cauer filter.

$\begin{matrix} {\frac{V_{out}}{V_{in}} = \frac{{b_{0}s^{n}} + {b_{2}s^{n - 2}} + \ldots + {b_{n - 3}s^{3}} + {b_{n - 1}s}}{{a_{0}s^{n}} + {a_{1}s^{n - 1}} + {a_{2}s^{n - 2}} + {\ldots \mspace{14mu} a_{n - 2}s^{2}} + {a_{n - 1}s} + a_{n}}} & (2) \end{matrix}$

Note that all the orders of the terms in the numerator of equation (1) and equation (2) are complementary each other. It is apparent that the Cauer filter realized from equation (1) cannot supply high-pass signals, secured from the one realized from equation (2). In order to be consistent with the term order, all the subscripts of the coefficients in equation (2) have been replaced and shown in equation (3).

$\begin{matrix} {\frac{V_{out}}{V_{in}} = \frac{{b_{n}s^{n}} + {b_{n - 2}s^{n - 2}} + \ldots + {b_{3}s^{3}} + {b_{1}s}}{{a_{n}s^{n}} + {a_{n - 1}s^{n - 1}} + {a_{n - 2}s^{n - 2}} + {\ldots \mspace{14mu} a_{2}s^{2}} + {a_{1}s} + a_{n}}} & (3) \end{matrix}$

Cross multiplying equation (3), dividing it by a_(n)s^(n), and re-arranging yield

$\begin{matrix} {{{{V_{out}(1)} - {V_{in}\left( \frac{b_{n}}{a_{n}} \right)}} = {{V_{in}\left( {\frac{b_{n - 2}}{a_{n}s^{2}} + \ldots + \frac{b_{3}}{a_{n}s^{n - 3}} + \frac{b_{1}}{a_{n}s^{n - 1}}} \right)} - {V_{out}\left( {\frac{a_{n - 1}}{a_{n}s} + \frac{a_{n - 2}}{a_{n}s^{2}} + \ldots + \frac{a_{1}}{a_{n}s^{n - 1}} + \frac{a_{0}}{a_{n}s^{n}}} \right)}}}\mspace{79mu} {Since}} & (4) \\ {\mspace{79mu} {{\left( \frac{a_{j}}{a_{n}} \right) = {\prod\limits_{j}^{n - 1}\; \left( \frac{a_{j}}{a_{j + 1}} \right)}}\mspace{85mu} {for}\mspace{79mu} {{j = 0},1,\ldots \mspace{14mu},{{n - 1};}}\mspace{79mu} {and}}} & (5) \\ {\mspace{79mu} {{\left( \frac{b_{j}}{a_{n}} \right) = {\left\lbrack {\prod\limits_{j}^{n - 1}\; \left( \frac{a_{j}}{a_{j + 1}} \right)} \right\rbrack \left( \frac{b_{j}}{a_{j}} \right)}}\mspace{79mu} {for}\mspace{79mu} {{j = 1},3,\ldots \mspace{14mu},{n - 2}}}} & (6) \end{matrix}$

Recombinations for some terms in equation (4) are presented as follows.

$\begin{matrix} {{{V_{in}\left( \frac{b_{n - 2}}{a_{n}s^{2}} \right)} - {V_{out}\left( {\frac{a_{n - 1}}{a_{n}s} + \frac{a_{n - 2}}{a_{n}s^{2}}} \right)}} = {\left( \frac{a_{n - 1}}{a_{n}s} \right)\left\lbrack {{- {V_{out}(1)}} + {\left( \frac{a_{n - 2}}{a_{n - 1}s} \right)\left\lbrack {{- {V_{out}(1)}} + \left( \frac{b_{n - 2}}{a_{n - 2}} \right)} \right\rbrack}} \right\rbrack}} & (7) \\ {{{V_{in}\left( \frac{b_{n - 4}}{a_{n}s^{4}} \right)} - {V_{out}\left( {\frac{a_{n - 3}}{a_{n}s^{3}} + \frac{a_{n - 4}}{a_{n}s^{4}}} \right)}} = {\left( \frac{a_{n - 2}}{a_{n}s^{2}} \right){\left( \frac{a_{n - 3}}{a_{n - 2}s} \right)\left\lbrack {{- {V_{out}(1)}} + {\left( \frac{a_{n - 4}}{a_{n - 3}s} \right)\left\lbrack {{- {V_{out}(1)}} + {V_{in}\left( \frac{b_{n - 4}}{a_{n - 4}} \right)}} \right\rbrack}} \right\rbrack}}} & (8) \\ {{{V_{in}\left( \frac{b_{1}}{a_{n}s^{n - 1}} \right)} - {V_{out}\left( {\frac{a_{2}}{a_{n}s^{n - 2}} + \frac{a_{1}}{a_{n}s^{n - 1}} + \frac{a_{0}}{a_{n}s^{n}}} \right)}} = {\left( \frac{a_{3}}{a_{n}s^{n - 3}} \right){\left( \frac{a_{2}}{a_{3}s} \right)\left\lbrack {{- {V_{out}(1)}} + {\left( \frac{a_{1}}{a_{2}s} \right)\left\lbrack {{- {V_{out}(1)}} + {V_{in}\left( \frac{b_{1}}{a_{1}} \right)} - {V_{out}\left( \frac{a_{0}}{a_{1}s} \right)}} \right\rbrack}} \right\rbrack}}} & (9) \end{matrix}$

Hence, equation (4) may be decomposed and combined as the following form.

$\begin{matrix} {{{V_{out}(1)} - {V_{in}\left( \frac{b_{n}}{a_{n}} \right)}} = {\left( \frac{a_{n - 1}}{a_{n}s} \right)\left\lbrack {{- {V_{out}(1)}} + {\left( \frac{a_{n - 2}}{a_{n - 1}s} \right)\left\lbrack {{- {V_{out}(1)}} + {V_{in}\left( \frac{b_{n - 2}}{a_{n - 2}} \right)} + {\left( \frac{a_{n - 3}}{a_{n - 2}s} \right)\left\lbrack {{- {V_{out}(1)}} + {\left( \frac{a_{n - 4}}{a_{n - 3}s} \right)\left\lbrack {\ldots + {\ldots \left\lbrack {{- {V_{out}(1)}} + {V_{in}\left( \frac{b_{3}}{a_{3}} \right)} + {\left( \frac{a_{2}}{a_{3}s} \right)\left\lbrack {{- {V_{out}(1)}} + {\left( \frac{a_{1}}{a_{2}s} \right)\left\lbrack {{- {V_{out}(1)}} + {V_{in}\left( \frac{b_{1}}{a_{1}} \right)} + {\left( \frac{a_{0}}{a_{1}s} \right)\left( {- {V_{out}(1)}} \right)}} \right\rbrack}} \right\rbrack}} \right\rbrack}} \right\rbrack}} \right\rbrack}} \right\rbrack}} \right\rbrack}} & (10) \end{matrix}$

Therefore, we may let

$\begin{matrix} {V_{1} = {\frac{1}{s}\left( {- {V_{out}(1)}} \right)}} & (11) \\ {V_{2} = {\frac{1}{s}\left( {{- {V_{out}(1)}} + {V_{in}\left( \frac{b_{1}}{a_{1}} \right)} + {V_{1}\left( \frac{a_{0}}{a_{1}} \right)}} \right)}} & (12) \\ {{V_{3} = {\frac{1}{s}\left( {{- {V_{out}(1)}} + {V_{2}\left( \frac{a_{1}}{a_{2}} \right)}} \right)}}\ldots} & (13) \\ {V_{n - 1} = {\frac{1}{s}\left( {{- {V_{out}(1)}} + {V_{in}\left( \frac{b_{n - 2}}{a_{n - 2}} \right)} + {V_{n - 2}\left( \frac{a_{n - 3}}{a_{n - 2}} \right)}} \right)}} & (14) \\ {V_{n} = {\frac{1}{s}\left( {{- {V_{out}(1)}} + {V_{n - 1}\left( \frac{a_{n - 2}}{a_{n - 1}} \right)}} \right)}} & (15) \\ {{{V_{out}(1)} - {V_{in}\left( \frac{b_{n}}{a_{n}} \right)}} = {V_{n}\left( \frac{a_{n - 1}}{a_{n}} \right)}} & (16) \end{matrix}$

Therefore, the transfer function (1) has been decomposed, using a series of algebraic manipulations, into the above simple equations, from equation (11) to equation (15). Observing equation (11) to equation (15), the configuration of equation (15) includes the others. Hence, we present the typical two OTRA-C based sub-circuitries realized from equation (14) and equation (16), both of which are shown in FIGS. 1A-1B and FIGS. 2A-2B, respectively.

Referring to FIGS. 1A-1B, which show the kth OTRA based sub-circuitries respectively, and k=2, 4, . . . , n−1 and n is an odd number, the main difference between the kth OTRA based sub-circuitries in FIGS. 1A-1B is the position of the capacitor arranged out of or in a feedback loop. Referring to FIGS. 2A-2B, FIGS. 2A-2B show two different realizations for the n+1th OTRA based sub-circuitry.

Referring to FIG. 3A and FIG. 3B, the combinations of all the n sub-circuitries realized from equations (11) to (16) are respectively shown in FIG. 3A and FIG. 3B, which are elliptic OTRA-C based voltage-mode odd-nth-order high-pass Cauer filter. Therefore, according to the analytical synthesis method mentioned above, the elliptic OTRA-C based voltage-mode odd-nth-order high-pass Cauer filter can be realized by the use of n+1 OTRAs and n capacitors.

To illustrate the synthesis method, consider the structure generation of a third order filter. The synthesis method uses equations (11), (14), (15) and (16). Based on these equations, when n=3, the following equations may be obtained:

$\begin{matrix} {V_{1} = {\frac{1}{s}\left( {- {V_{out}(1)}} \right)}} & (17) \\ {V_{2} = {\frac{1}{s}\left( {{- {V_{out}(1)}} + {V_{in}\left( \frac{b_{1}}{a_{1}} \right)} + {V_{1}\left( \frac{a_{0}}{a_{1}} \right)}} \right)}} & (18) \\ {V_{3} = {\frac{1}{s}\left( {{- {V_{out}(1)}} + {V_{2}\left( \frac{a_{1}}{a_{2}} \right)}} \right)}} & (19) \\ {{{V_{out}(1)} - {V_{in}\left( \frac{b_{3}}{a_{3}} \right)}} = {V_{3}\left( \frac{a_{2}}{a_{3}} \right)}} & (20) \end{matrix}$

Therefore, the combination of the four OTRA-C based sub-circuitries realized from equations (17) to (20) are respectively shown in FIG. 4A and FIG. 4B, which are elliptic OTRA-based third-order high-pass Cauer filter.

Embodiment 2

Different from the above analytical synthesis, another approach for analytically synthesizing the transfer function (3) is shown as follows.

Cross multiplying the transfer function (3) and dividing it by s^(n-1) yield

$\begin{matrix} {{V_{out}\left\lbrack {\left( {{a_{n}s} + a_{n - 1}} \right) + \frac{a_{n - 2}}{s} + \ldots + \underset{\_}{\underset{\_}{\frac{a_{3}}{s^{n - 4}}}} + \underset{\_}{\frac{a_{2}}{s^{{n - 3}\;}}} + \left( {\frac{a_{1}}{s^{n - 2}} + \frac{a_{0}}{s^{n - 1}}} \right)} \right\rbrack} = {V_{in}\left\lbrack {\left( {a_{n}s} \right) + \frac{b_{n - 2}}{s} + \ldots + \underset{\_}{\underset{\_}{\frac{b_{3}}{s^{n - 4}}}} + \left( \frac{b_{1}}{s^{n - 2}} \right)} \right\rbrack}} & (29) \end{matrix}$

Combine the last two terms of the left side and the last term of the right side of equation (21) as

$\begin{matrix} {{{V_{in}\left( \frac{b_{1}}{s^{n - 2}} \right)} - {V_{out}\left( {\frac{a_{1}}{s^{n - 2}} + \frac{a_{0}}{s^{n - 1}}} \right)}} = {\left( \frac{1}{s^{n - 2}} \right)\left\lbrack {{V_{in}\left( b_{1} \right)} - {V_{out}\left( {a_{1} + \frac{a_{0}}{s}} \right)}} \right\rbrack}} & (22) \end{matrix}$

Add the last third term of the left side of equations (21) to (22) and arrange them as

$\begin{matrix} {{{\left( \frac{1}{s^{n - 2}} \right)\left\lbrack {{V_{in}\left( b_{1} \right)} - {V_{out}\left( {a_{1} + \frac{a_{0}}{s}} \right)}} \right\rbrack} - {V_{out}\left( \frac{a_{2}}{s^{n - 3}} \right)}} = {\left( \frac{1}{s^{n - 3}} \right)\left\lbrack {{\left( \frac{1}{s} \right)\left\lbrack {{V_{in}\left( b_{1} \right)} - {V_{out}\left( {a_{1} + \frac{a_{0}}{s}} \right)}} \right\rbrack} - {V_{out}\left( a_{2} \right)}} \right\rbrack}} & (23) \end{matrix}$

Add the last fourth terms of the left side and the last second term of the right side of equations (21) to (23) and re-arrange them as

$\begin{matrix} {{{\left( \frac{1}{s^{n - 3}} \right)\left\lbrack {{\left( \frac{1}{s} \right)\left\lbrack {{V_{in}\left( b_{1} \right)} - {V_{out}\left( {a_{1} + \frac{a_{0}}{s}} \right)}} \right\rbrack} - {V_{out}\left( a_{2} \right)}} \right\rbrack} + {V_{in}\left( \frac{b_{3}}{s^{{n - 4}\;}} \right)} - {V_{out}\left( \frac{a_{3}}{s^{n - 4}} \right)}} = {\left( \frac{1}{s^{n - 4}} \right)\left\lbrack {{\left( \frac{1}{s} \right)\left\lbrack {{\left( \frac{1}{s} \right)\left\lbrack {{V_{in}\left( b_{1} \right)} - {V_{out}\left( {a_{1} + \frac{a_{0}}{s}} \right)}} \right\rbrack} - {V_{out}\left( a_{2} \right)}} \right\rbrack} + {V_{in}\left( b_{3} \right)} - {V_{out}\left( a_{3} \right)}} \right\rbrack}} & (24) \end{matrix}$

Continue the above combinations and arrangements for the other terms of equation (21) and then equation (21) may be decomposed as

$\begin{matrix} {{V_{out}\left( {{a_{n}s} + a_{n - 1}} \right)} = {{V_{in}\left( {a_{n}s} \right)} = {\left( \frac{1}{s} \right)\left\lbrack {\left( \frac{1}{s} \right) + {V_{in}\left( b_{n - 2} \right)} - {{V_{out}\left( a_{n - 2} \right)}\left\lbrack {\left( \frac{1}{s} \right) - {{V_{out}\left( a_{n - 3} \right)}\left\lbrack {\left( \frac{1}{s} \right) + {V_{in}\left( b_{n - 4} \right)} - {{V_{out}\left( a_{n - 4} \right)}\left\lbrack {\ldots + {\ldots \left\lbrack {\left( \frac{1}{s} \right) + {V_{in}\left( b_{3} \right)} - {{V_{out}\left( a_{3} \right)}\left\lbrack {\left( \frac{1}{s} \right) - {{V_{out}\left( a_{2} \right)}\left\lbrack {{V_{in}\left( b_{1} \right)} - {V_{out}\left( {a_{1} + \frac{a_{0}}{s}} \right)}} \right\rbrack}} \right\rbrack}} \right\rbrack}} \right\rbrack}} \right\rbrack}} \right\rbrack}} \right\rbrack}}} & (25) \end{matrix}$

Therefore, we may let

$\begin{matrix} {{V_{1} = {{- \left( \frac{a_{0}}{s} \right)}V_{out}}},{i.e.},{{V_{1}\left( \frac{s}{a_{0}} \right)} = {- {V_{out}(1)}}}} & (26) \\ {{V_{2}\left( \frac{s}{a_{1}} \right)} = {{V_{in}\left( \frac{b_{1}}{a_{1}} \right)} - {V_{out}(1)} + {V_{1}\left( \frac{1}{a_{1}} \right)}}} & (27) \\ {{V_{3}\left( \frac{s}{a_{2}} \right)} = {{- {V_{out}(1)}} + {V_{2}\left( \frac{1}{a_{2}} \right)}}} & (28) \\ {{{V_{4}\left( \frac{s}{a_{3}} \right)} = {{V_{in}\left( \frac{b_{3}}{a_{3}} \right)} - {V_{out}(1)} + {V_{3}\left( \frac{1}{a_{3}} \right)}}}\ldots} & (29) \\ {{V_{n - 2}\left( \frac{s}{a_{n - 3}} \right)} = {{- {V_{out}(1)}} + {V_{n - 3}\left( \frac{1}{a_{n - 3}} \right)}}} & (30) \\ {{{V_{n - 1}\left( \frac{s}{a_{n - 2}} \right)} = {{V_{in}\left( \frac{b_{n - 2}}{a_{n - 2}} \right)} - {V_{out}(1)} + {V_{n - 2}\left( \frac{1}{a_{{n - 2}\;}} \right)}}}{And}{{{V_{out}\left( {{a_{n}s} + a_{n - 1}} \right)} = {{V_{in}\left( {a_{n}s} \right)} + {V_{n - 1}(1)}}},{i.e.},}} & (31) \\ {{V_{out}\left( {\frac{a_{n\;}s}{a_{n - 1}} + 1} \right)} = {{V_{in}\left( \frac{a_{n}s}{a_{n - 1}} \right)} + {V_{n - 1}\left( \frac{1}{a_{n - 1}} \right)}}} & (32) \end{matrix}$

Observing equations (26) to (31), all the simple equations from equations (26) to (31) may be represented by a typical equation (31). The OTRA-C based sub-circuitries realized from equations (31) and (32) are shown in FIGS. 5A-5B and FIGS. 6A-6B, respectively.

Referring to FIGS. 5A-5B, which show the kth OTRA based sub-circuitries respectively and k=2, 4, . . . , n−1, the main difference between the kth OTRA based sub-circuitries in FIGS. 5A-5B is the position of the capacitor arranged out of or in a feedback loop. As for FIGS. 6A-6B, FIGS. 6A-6B respectively illustrate two different realizations for the nth OTRA based sub-circuitry.

Based upon these two typical realized sub-circuitries, all of the simple equations are easily realizable. The superposition of all the realized OTRA-C based sub-circuitries constructs the second elliptic OTRA-C based voltage-mode odd-nth-order high-pass Cauer filter structures which are respectively shown in FIGS. 7A-7B. Therefore, according to the analytical synthesis method mentioned above, the elliptic OTRA-C based voltage-mode odd-nth-order high-pass Cauer filter can be realized by the use of n OTRAs and n+1 capacitors.

To illustrate the synthesis method, consider the structure generation of a third order filter. The synthesis method uses equations (26), (31), and (32). Based on these equations, when n=3, the following equations may be obtained:

$\begin{matrix} {{V_{1}\left( \frac{s}{a_{0}} \right)} = {- {V_{out}(1)}}} & (33) \\ {{V_{2}\left( \frac{s}{a_{1}} \right)} = {{V_{in}\left( \frac{b_{1}}{a_{1}} \right)} - {V_{out}(1)} + {V_{1}\left( \frac{1}{a_{1}} \right)}}} & (34) \\ {{V_{out}\left( {\frac{a_{3}s}{a_{2}} + 1} \right)} = {{V_{in}\left( \frac{a_{3}s}{a_{2}} \right)} + {V_{2}\left( \frac{1}{a_{2}} \right)}}} & (35) \end{matrix}$

Consequently, the combination of the three OTRA-C based sub-circuitries realized from the above three equations is an elliptic third-order OTRA-C based high-pass Cauer filter which may be realized as shown in FIGS. 8A-8B.

Embodiment 3

Consider again the elliptic odd-nth-order Cauer filter given by (1). Cross-multiplying (1), then dividing both sides of the resulting equation by a_(n)s^(n-1), we can show that

$\begin{matrix} {{\left( {s + \frac{a_{n - 1}}{a_{n}} + \frac{a_{n - 2}}{a_{n}s} + \ldots + \frac{a_{2}}{a_{n}s^{n - 3}} + \frac{a_{1}}{a_{n}s^{n - 2}} + \frac{a_{0}}{a_{n}s^{n - 1}}} \right)V_{out}} = {\left( {\frac{b_{n - 1}}{a_{n}} + \frac{b_{n - 2}}{a_{n}s^{2}} + \ldots + \frac{b_{2}}{a_{n}s^{n - 3}} + \frac{b_{0}}{a_{n}s^{n - 1}}} \right)V_{in}}} & (36) \end{matrix}$

By re-arranging, we may write (36) as

$\begin{matrix} {{{\left( {s + \frac{a_{n - 1}}{a_{n}}} \right)V_{out}} - {\left( \frac{b_{n - 1}}{a_{n}} \right)V_{i\; n}}} = {{\frac{1}{s}\left( {- \frac{a_{n - 2}}{a_{n}}} \right)V_{out}} + {\frac{1}{s^{2}}\left( {{\frac{b_{n - 3}}{a_{n}}V_{i\; n}} - {\frac{a_{n - 3}}{a_{n}}V_{out}}} \right)} + {\frac{1}{s^{3}}\left( {- \frac{a_{n - 4}}{a_{n}}} \right)V_{out}} + {\frac{1}{s^{4}}\left( {{\frac{b_{n - 5}}{a_{n}}V_{i\; n}} - {\frac{a_{n - 5}}{a_{n}}V_{out}}} \right)} + \ldots + \ldots + {{\cdot \frac{1}{s^{n - 2}}}\left( {- \frac{a_{1}}{a_{n}}} \right)V_{out}} + {\frac{1}{s^{n - 1}}\left( {{\frac{b_{0}}{a_{n}}V_{i\; n}} - {\frac{a_{0}}{a_{n}}V_{out}}} \right)}}} & (37) \end{matrix}$

This may be re-written as

$\begin{matrix} {{{\left( {s + \frac{a_{n - 1}}{a_{n}}} \right)V_{out}} - {\left( \frac{b_{n - 1}}{a_{n}} \right)V_{i\; n}}} = {\left( \frac{1}{s} \right)\left( {{{- \frac{a_{n - 2}}{a_{n}}}V_{out}} + {\left( \frac{1}{s} \right)\left( {{\frac{b_{n - 3}}{a_{n}}V_{i\; n}} - {\frac{a_{n - 3}}{a_{n}}V_{out}} + {\left( \frac{1}{s} \right)\left( {{{- \frac{a_{n - 4}}{a_{n}}}V_{out}} + \ldots + {\left( \frac{1}{s} \right)\left( {{{- \frac{a_{1}}{a_{n}}}V_{out}} + {\left( \frac{1}{s} \right)\left( {{\frac{b_{0}}{a_{n}}V_{i\; n}} - {\frac{a_{0}}{a_{n}}V_{out}}} \right)}} \right)\mspace{14mu} \ldots}}\mspace{14mu} \right)}} \right)}} \right)}} & (38) \end{matrix}$

Based on the above, we may write the following relations.

$\begin{matrix} {V_{0} = {\left( \frac{1}{s} \right)\left( {{\frac{b_{0}}{a_{n}}V_{i\; n}} - {\frac{a_{0}}{a_{n}}V_{out}}} \right)}} & (39.0) \\ {{V_{j} = {{\left( \frac{1}{s} \right)\left( {V_{j - 1} - {\frac{a_{j}}{a_{n}}V_{out}}} \right)\mspace{14mu} {for}\mspace{14mu} j} = 1}},3,5,\ldots \mspace{14mu},{n - 2.}} & \left( {39.j} \right) \\ {{{V_{k} = {\left( \frac{1}{s} \right)\left( {V_{k - 1} + {\frac{b_{k}}{a_{n}}V_{i\; n}} - {\frac{a_{k}}{a_{n}}V_{out}}} \right)}}{{{for}\mspace{14mu} k} = 2},4,6,\ldots \mspace{14mu},{n - 3}}{and}} & \left( {39.k} \right) \\ {{{\left( {s + \frac{a_{n - 1}}{a_{n}}} \right)V_{out}} - {\left( \frac{b_{n - 1}}{a_{n}} \right)V_{i\; n}}} = V_{n - 2}} & \left( {39.n\text{-}1} \right) \end{matrix}$

Therefore, the transfer function (1) has been decomposed, using a series of algebraic manipulations, into the above n simple equations, from (39.0) to (39.n−1), each of which is easily realizable by a single OTRA, a capacitor, and several resistors. The combination of all the n sub-circuitries obtained from (39.0) to (39.n−1) is shown in FIG. 9, which is another OTRA-RC structure realizing the odd-nth-order elliptic Cauer filter structure given by (1). There are n OTRAs, n capacitors, and (5n−1)/2 resistors employed in the realization.

Let us consider the particular case when n=3; based upon the relations (39), we obtain the following three simple equations.

$\begin{matrix} {V_{0} = {\left( \frac{1}{s} \right)\left( {{\frac{b_{0}}{a_{3}}V_{i\; n}} - {\frac{a_{0}}{a_{3}}V_{out}}} \right)}} & (40.0) \\ {{V_{1} = {\left( \frac{1}{s} \right)\left( {V_{0} - {\frac{a_{1}}{a_{3}}V_{out}}} \right)}}{and}} & (40.1) \\ {{{\left( {s + \frac{a_{2}}{a_{3}}} \right)V_{out}} - {\left( \frac{b_{2}}{a_{3}} \right)V_{i\; n}}} = V_{1}} & (40.2) \end{matrix}$

Superposing these three sub-circuitries realized from (40.0), (40.1), and (402), a third-order elliptic Cauer filter is obtained, as shown in FIG. 10. The dashed blocks in FIG. 10 show the three corresponding sub-circuitries realized from (40.0), (40.1), and (40.2), where the component values are given by C1=C2=C3=1 F, G1=a2/a3

, G2=a1/a3

, G3=a0/a3

, G4=1

, G5=1

, G6=b2/a3

, and G7=b0/a3

. Note that the synthesized elliptic Cauer filter structure uses equal capacitors, thus avoiding the difficulty of realizing precise values of different capacitors in an integrated circuit.

Then, in the following embodiments, two analytical synthesis methods (ASMs) will be presented for the realization of two even-nth-order elliptic Cauer filters, which have the following main difference: one uses “n+1” OTRAs and “n” capacitors and the other employs “n” OTRAs and “n+1” capacitors.

Embodiment 4

The transfer function of a conventional elliptic voltage-mode even-nth-order Cauer filter which produces only low-pass signals is given by

$\begin{matrix} {\frac{V_{out}}{V_{i\; n}} = \frac{{b_{n}s^{n}} + {b_{n - 2}s^{n - 2}} + \ldots + {b_{2}s^{2}} + b_{0}}{{a_{n}s^{n}} + {a_{n - 1}s^{n - 1}} + {a_{n - 2}s^{n - 2}} + \ldots + {a_{2}s^{2}} + {a_{1}s} + a_{0}}} & (41) \end{matrix}$

Cross multiplying (41), then dividing both sides by a_(n)s^(n-1), and rearranging the terms just as we did in the above embodiment, we obtain

$\begin{matrix} {{{\left( {s + \frac{a_{n - 1}}{a_{n}}} \right)V_{out}} - {\left( {\frac{b_{n}}{a_{n}}s} \right)V_{i\; n}}} = {{\frac{1}{s}\left( {{\frac{b_{n - 2}}{a_{n}}V_{i\; n}} - {\frac{a_{n - 2}}{a_{n}}V_{out}}} \right)} + {\frac{1}{s^{2}}\left( {- \frac{a_{n - 3}}{a_{n}}} \right)V_{out}} + {\frac{1}{s^{3}}\left( {{\frac{b_{n - 4}}{a_{n}}V_{i\; n}} - {\frac{a_{n - 4}}{a_{n}}V_{out}}} \right)} + {\frac{1}{s^{4}}\left( {- \frac{a_{n - 5}}{a_{n}}} \right)V_{out}} + \ldots + {\frac{1}{s^{n - 2}}\left( {- \frac{a_{1}}{a_{n}}} \right)V_{out}} + {\frac{1}{s^{n - 1}}\left( {{\frac{b_{0}}{a_{n}}V_{i\; n}} - {\frac{a_{0}}{a_{n}}V_{out}}} \right)}}} & (42) \end{matrix}$

Equation (42) may be re-written as

$\begin{matrix} {{{\left( {s + \frac{a_{n - 1}}{a_{n}}} \right)V_{out}} - {\left( {\frac{b_{n}}{a_{n}}s} \right)V_{i\; n}}} = {\left( \frac{1}{s} \right)\left( {{\frac{b_{n - 2}}{a_{n}}V_{i\; n}} - {\frac{a_{n - 2}}{a_{n}}V_{out}} + {\left( \frac{1}{s} \right)\left( {{{- \frac{a_{n - 3}}{a_{n}}}V_{out}} + {\left( \frac{1}{s} \right)\left( {{\frac{b_{n - 4}}{a_{n}}V_{i\; n}} - {\frac{a_{n - 4}}{a_{n}}V_{out}} + \ldots + {\left( \frac{1}{s} \right)\left( {{{- \frac{a_{1}}{a_{n}}}V_{out}} + {\left( \frac{1}{s} \right)\left( {{\frac{b_{0}}{a_{n}}V_{i\; n}} - {\frac{a_{0}}{a_{n}}V_{out}}} \right)}} \right)\mspace{14mu} \ldots}}\mspace{14mu} \right)}} \right)}} \right)}} & (43) \end{matrix}$

Based on the above equation, we may write the following relations.

$\begin{matrix} {V_{0} = {\left( \frac{1}{s} \right)\left( {{\frac{b_{0}}{a_{n}}V_{i\; n}} - {\frac{a_{0}}{a_{n}}V_{out}}} \right)}} & (44.0) \\ {{V_{j} = {{\left( \frac{1}{s} \right)\left( {V_{j - 1} - {\frac{a_{j}}{a_{n}}V_{out}}} \right)\mspace{14mu} {for}\mspace{14mu} j} = 1}},3,5,\ldots \mspace{14mu},{n - 3.}} & \left( {44.j} \right) \\ {{{V_{k} = {\left( \frac{1}{s} \right)\left( {V_{k - 1} + {\frac{b_{k}}{a_{n}}V_{i\; n}} - {\frac{a_{k}}{a_{n}}V_{out}}} \right)}}{{{for}\mspace{14mu} k} = 2},4,6,\ldots \mspace{14mu},{n - 2}}{and}} & \left( {44.k} \right) \\ {{{\left( {s + \frac{a_{n - 1}}{a_{n}}} \right)V_{out}} - {\left( {\frac{b_{n - 1}}{a_{n}}s} \right)V_{i\; n}}} = V_{n - 2}} & \left( {44.n\text{-}1} \right) \end{matrix}$

Therefore, the transfer function (41) has been decomposed, using a series of algebraic manipulations, into the above n simple equations, from (44.0) to (44.n−1). Each of the above n equations can be realized using a single OTRA, one capacitor and several resistors, except for (44.n−1) for which two capacitors are required. The combination of all the n sub-circuitries realized from (44.0) to (44.n−1) is shown in FIG. 11, which is an OTRA-RC structure realizing the even-nth-order elliptic Cauer filter given by (41). There are n OTRAs, n+1 capacitors, and (5n−2)/2 resistors employed in the realization.

Let us consider the case when n=4; based upon the relations (44), we obtain the following three simple relations.

$\begin{matrix} {V_{0} = {\left( \frac{1}{s} \right)\left( {{\frac{b_{0}}{a_{4}}V_{i\; n}} - {\frac{a_{0}}{a_{4}}V_{out}}} \right)}} & (45.0) \\ {V_{1} = {\left( \frac{1}{s} \right)\left( {V_{0} - {\frac{a_{1}}{a_{4}}V_{out}}} \right)}} & (45.1) \\ {{V_{2} = {\left( \frac{1}{s} \right)\left( {V_{1} + {\frac{b_{2}}{a_{4}}V_{i\; n}} - {\frac{a_{2}}{a_{4}}V_{out}}} \right)}}{and}} & (45.2) \\ {{{\left( {s + \frac{a_{3}}{a_{4}}} \right)V_{out}} - {\left( {\frac{b_{4}}{a_{4}}s} \right)V_{i\; n}}} = V_{2}} & (45.3) \end{matrix}$

The synthesized sub-circuitries corresponding to (45.0)-(45.3) are shown in the dashed blocks in FIG. 12, the component values being C₁=C₂=C₃=C₄=1 F, C₁₁=(b₄/a₄)F, G₁=(a₁/a₄)

, G₂=(a₂/a₄)

, G₃=(a₁/a₄)

, G₄=(a₀/a₄)

, G₅=G₆=G₇=1

, G₂₂=(b₂/a₄)

, and G₄₄=(b₀/a₄)

.

Embodiment 5

Consider again the elliptic Cauer even-nth-order filter given by (41). Cross-multiplying (41), then dividing both sides of the resulting equation by a_(n)s^(n) and rearranging it, we can show that

$\begin{matrix} {{V_{out} - {\left( \frac{b_{n}}{a_{n}} \right)V_{i\; n}}} = {{\frac{1}{s}\left( {- \frac{a_{n - 1}}{a_{n}}} \right)V_{out}} + {\frac{1}{s^{2}}\left( {{\frac{b_{n - 3}}{a_{n}}V_{i\; n}} - {\frac{a_{n - 3}}{a_{n}}V_{out}}} \right)} + {\frac{1}{s^{3}}\left( {- \frac{a_{n - 3}}{a_{n}}} \right)V_{out}} + {\frac{1}{s^{4}}\left( {{\frac{b_{n - 4}}{a_{n}}V_{i\; n}} - {\frac{a_{n - 4}}{a_{n}}V_{out}}} \right)} + \ldots + \ldots + {{\cdot \frac{1}{s^{n - 1}}}\left( {- \frac{a_{1}}{a_{n}}} \right)V_{out}} + {\frac{1}{s^{n}}\left( {{\frac{b_{0}}{a_{n}}V_{i\; n}} - {\frac{a_{0}}{a_{n}}V_{out}}} \right)}}} & (46) \end{matrix}$

The above equation may be re-written as

$\begin{matrix} {{V_{out} - {\left( \frac{b_{n}}{a_{n}} \right)V_{i\; n}}} = {\left( \frac{1}{s} \right)\left( {{{- \frac{a_{n - 1}}{a_{n}}}V_{out}} + {\left( \frac{1}{s} \right)\left( {{\frac{b_{n - 2}}{a_{n}}V_{i\; n}} - {\frac{a_{n - 2}}{a_{n}}V_{out}} + {\left( \frac{1}{s} \right)\left( {{{- \frac{a_{n - 3}}{a_{n}}}V_{out}} + \ldots + \left. \quad{\left( \frac{1}{s} \right)\left( {{{- \frac{a_{1}}{a_{n}}}V_{out}} + {\left( \frac{1}{s} \right)\left( {{\frac{b_{0}}{a_{n}}V_{i\; n}} - {\frac{a_{0}}{a_{n}}V_{out}}} \right)}} \right)\mspace{14mu} \ldots}\mspace{14mu} \right)} \right)}} \right)}} \right.}} & (47) \end{matrix}$

Based on (47), we may write the following relations.

$\begin{matrix} {V_{0} = {\left( \frac{1}{s} \right)\left( {{\frac{b_{0}}{a_{n}}V_{i\; n}} - {\frac{a_{0}}{a_{n}}V_{out}}} \right)}} & (48.0) \\ {{V_{j} = {{\left( \frac{1}{s} \right)\left( {V_{j - 1} - {\frac{a_{j}}{a_{n}}V_{out}}} \right)\mspace{14mu} {for}\mspace{14mu} j} = 1}},3,5,\ldots \mspace{14mu},{n - 1}} & \left( {48.j} \right) \\ {{{V_{k} = {\left( \frac{1}{s} \right)\left( {V_{k - 1} + {\frac{b_{k}}{a_{n}}V_{i\; n}} - {\frac{a_{k}}{a_{n}}V_{out}}} \right)}}{{{for}\mspace{14mu} k} = 2},4,6,\ldots \mspace{14mu},{n - 2}}{and}} & \left( {48.k} \right) \\ {{V_{out} - {\left( \frac{b_{n}}{a_{n}} \right)V_{i\; n}}} = V_{n - 1}} & \left( {48.n} \right) \end{matrix}$

Therefore, the transfer function (41) has been decomposed, using a series of algebraic manipulations, into the above n+1 simple equations, from (48.0) to (48.n). Each of these n+1 equations can be realized using a single OTRA, one capacitor and several resistors, except for (48.n) which needs no capacitor. The combination of all the n+1 sub-circuitries realized from (48.0) to (48.n) is shown in FIG. 13, which is a second OTRA-RC structure realizing the even-nth-order elliptic Cauer filter given by (41). There are n+1 OTRAs, n capacitors, and (5n−2)/2 resistors employed in the realization.

Let us again consider the case when n=4; based upon the relations (48), we obtain the following three simple relations.

$\begin{matrix} {V_{0} = {\left( \frac{1}{s} \right)\left( {{\frac{b_{0}}{a_{4}}V_{i\; n}} - {\frac{a_{0}}{a_{4}}V_{out}}} \right)}} & (49.0) \\ {V_{1} = {\left( \frac{1}{s} \right)\left( {V_{0} - {\frac{a_{1}}{a_{4}}V_{out}}} \right)}} & (49.1) \\ {V_{2} = {\left( \frac{1}{s} \right)\left( {V_{1} + {\frac{b_{2}}{a_{4}}V_{i\; n}} - {\frac{a_{2}}{a_{4}}V_{out}}} \right)}} & (49.2) \\ {{V_{3} = {\left( \frac{1}{s} \right)\left( {V_{2} - {\frac{a_{3}}{a_{4}}V_{out}}} \right)}}{and}} & (49.3) \\ {{V_{out} - {\left( \frac{b_{4}}{a_{4}} \right)V_{i\; n}}} = V_{3}} & (49.4) \end{matrix}$

Equations (49.0)-(49.4) may easily be realized as five OTRA-based sub-circuitries shown in the dashed blocks in FIG. 14, the component values being, C₁=C₂=C₃=C=1 F, G₁=1

, G₂=a₃/a₄

, G₄=a₁/a₄

, G₃=a₂/a₄

, G₅=a₀/a₄

, G₆=1

, G₇=1

, G₈=1

, G₉=

, G₁₁=b₄/a₄

, G₃₃=b₂/a₄

, and G₅₅=b₀/a₄

. Note that all the four capacitors have the same value.

Note that the structure illustrated in embodiment 5 differs from the structure illustrated in embodiment 4. The even-nth-order elliptic Cauer filter of FIG. 11 uses n OTRAs and n+1 capacitors, whereas that of FIG. 13 employs n+1 OTRAs and n capacitors. From the point of view of the area of an integrated circuit, a capacitor in general has a much larger area than an OTRA with fourteen MOSFETs. The fourth-order filter of FIG. 12 is larger in IC area than the one of FIG. 14.

Since the two input terminals of an OTRA are virtually grounded, the resistor shown in FIGS. 1 to 14 may be replaced by two parallel NMOS transistors M1 and M2, as shown in FIG. 15, both of which are matched and operating in ohmic region. The current passing through an NMOS transistor is given by

$\begin{matrix} {I = {{{K_{N}\left( {V_{G} - V_{T}} \right)}\left( {V_{D} - V_{S}} \right)} + {\sum\limits_{i = 1}^{2}{a_{i}\left( {V_{D}^{\prime} - V_{s}^{\prime}} \right)}}}} & (53) \end{matrix}$

The transistors M1 and M2 have the same drain and source voltages leading to the cancellation of the odd and even nonlinearities. The current difference shown in FIG. 15 is

$\begin{matrix} {{{I_{1} - I_{2}} = {G\left( {V_{1} - V_{2}} \right)}}{where}} & (54) \\ {G = {\mu_{N}C_{ox}\frac{W}{L}\left( {V_{a} - V_{b}} \right)}} & (55) \end{matrix}$

While the invention has been described by way of example and in terms of the preferred embodiment(s), it is to be understood that the invention is not limited thereto. On the contrary, it is intended to cover various modifications and similar arrangements and procedures, and the scope of the appended claims therefore should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements and procedures. 

1. An analytical synthesis method (ASM) for designing an higher-order voltage-mode elliptic operational trans-resistance amplifier and capacitor (OTRA-C) based filter, comprising: using a processor to perform the steps of: converting a decomposition of a complicated nth-order transfer function into a set of equations corresponding to a set of sub-circuitries; and constructing a circuit structure by combining said sub-circuitries, wherein the elliptic OTRA-C based filter comprises n OTRAs and n+1 capacitors to serve as an odd nth order voltage-mode elliptic OTRA-C based universal filter.
 2. The ASM for designing OTRA-C based filter according to claim 1, wherein the OTRA-C based filter comprises n+1 OTRAs and n capacitors to serve as an odd nth order voltage-mode OTRA-C based universal filter.
 3. The ASM for designing OTRA-C based filter according to claim 2, wherein the OTRA-C based filter comprises n+1 sub-circuitries and n is an odd number, and wherein each of the kth sub-circuitries, k=2, 4, . . . , n−1, comprises an OTRA having a negative input, a positive input and an output, and the output is connected to the negative input through a capacitor, and the negative input is connected to a voltage output terminal through a resistor, and the positive input is simultaneously connected to a voltage input terminal through a resistor and connected to an output of the OTRA of the k−1th sub-circuitry through a resistor.
 4. The ASM for designing OTRA-C based filter according to claim 3, wherein each of the jth sub-circuitries, j=3, 5, . . . , n, comprises an OTRA having a negative input, a positive input and an output, and the output is connected to the negative input through a capacitor, and the negative input is connected to the voltage output terminal through a resistor, and the positive input is connected to the output of OTRA of the j−1th sub-circuitry through a resistor.
 5. The ASM for designing OTRA-C based filter according to claim 4, wherein the n+1th sub-circuitry comprises an OTRA having a negative input, a positive input and an output, and the output is connected to the negative input through a resistor, and the positive input is simultaneously connected to the voltage input terminal through a resistor and connected to the output of the OTRA of the nth sub-circuitry through a resistor.
 6. The ASM for designing OTRA-C based filter according to claim 4, wherein the 1th sub-circuitry comprises an OTRA having a negative input, a positive input and an output, and the output is connected to the negative input through a capacitor, and the positive input is grounded, and the negative input is connected to the voltage output terminal through a resistor.
 7. The ASM for designing OTRA-C based filter according to claim 2, wherein the OTRA-C based filter comprises n+1 sub-circuitries and n is an odd number, and wherein each of the kth sub-circuitries, k=2, 4, . . . , n−1, comprises an OTRA having a negative input, a positive input and an output, and the output is connected to the negative input through a resistor, and the negative input is connected to a voltage input terminal through a resistor, and the positive input is simultaneously connected to a voltage output terminal through a resistor and connected to an output of the OTRA of the k−1th sub-circuitry through a capacitor.
 8. The ASM for designing OTRA-C based filter according to claim 7, wherein each of the jth sub-circuitries, j=3, 5, . . . , n, comprises an OTRA having a negative input, a positive input and an output, and the output is connected to the negative input through a resistor, and the positive input is simultaneously connected to the voltage output terminal through a resistor and connected to the output of OTRA of the j+1th sub-circuitry through a capacitor.
 9. The ASM for designing OTRA-C based filter according to claim 8, wherein the n+1th sub-circuitry comprises an OTRA having a negative input, a positive input and an output, and the output is connected to the negative input through a resistor, and the negative input is connected to the voltage input terminal through a resistor, and the positive input is connected to the voltage output terminal through a resistor.
 10. The ASM for designing OTRA-C based filter according to claim 8, wherein the 1th sub-circuitry comprises an OTRA having a negative input, a positive input and an output, and the output is connected to the negative input through a resistor, and the positive input is grounded, and the negative input is connected to the output of the OTRA of the 2th sub-circuitry through a capacitor.
 11. (canceled)
 12. The ASM for designing an elliptic OTRA-C based filter according to claim 1, wherein the elliptic OTRA-C based filter comprises n sub-circuitries and n is an odd number, and wherein each of the kth sub-circuitries, k=2, 4, . . . , n−1, comprises an OTRA having an negative input, an positive input and an output, and the output is connected to the negative input through a resistor, and the negative input is connected to a voltage input terminal through a resistor, and the positive input is simultaneously connected to a voltage output terminal through a resistor and connected to an output of the OTRA of the k+1th sub-circuitry through a capacitor.
 13. The ASM for designing an elliptic OTRA-C based filter according to claim 12, wherein each of the jth sub-circuitries, j=3, . . . , n−2, comprises an OTRA having an negative input, an positive input and an output, and the output is connected to the negative input through a resistor, and the positive input is simultaneously connected to the voltage output terminal through a resistor and connected to the output of the OTRA of the j+1th sub-circuitry through a capacitor.
 14. The ASM for designing an elliptic OTRA-C based filter according to claim 13, wherein the nth sub-circuitry comprises an OTRA having an negative input, an positive input and an output, and the output is connected to the negative input through a resistor, and the negative input is connected to the voltage input terminal through a capacitor, and the positive input is connected to the voltage output terminal through a resistor and a capacitor connected in parallel.
 15. The ASM for designing an elliptic OTRA-C based filter according to claim 13, wherein the 1th sub-circuitry comprises an OTRA having an negative input, an positive input and an output, and the output is connected to the negative input through a resistor, and the positive input is grounded, and the negative input is connected to the output of the OTRA of the 2th sub-circuitry through a capacitor.
 16. The ASM for designing an elliptic OTRA-C based filter according to claim 1, wherein the elliptic OTRA-C based filter comprises n sub-circuitries and n is an odd number, and wherein each of the kth sub-circuitries, k=2, 4, . . . , n−1, comprises an OTRA having an negative input, an positive input and an output, and the output is connected to the negative input through a capacitor, and the negative input is connected to a voltage output terminal through a resistor, and the positive input is simultaneously connected to a voltage input terminal through a resistor and connected to an output of the OTRA of the k−1th sub-circuitry through a resistor.
 17. The ASM for designing an elliptic OTRA-C based filter according to claim 16, wherein each of the jth sub-circuitries, j=3, . . . , n−2, comprises an OTRA having an negative input, an positive input and an output, and the output is connected to the negative input through a capacitor, and the negative input is connected to the voltage output terminal through a resistor, and the positive input is connected to the output of the OTRA of the j−1th sub-circuitry through a resistor.
 18. The ASM for designing an elliptic OTRA-C based filter according to claim 17, wherein the nth sub-circuitry comprises an OTRA having an negative input, an positive input and an output, and the output is connected to the negative input through a resistor and a capacitor connected in parallel, and the positive input is simultaneously connected to the voltage input terminal through a capacitor and connected to the output of the OTRA of the n−1th sub-circuitry through a resistor.
 19. The ASM for designing an elliptic OTRA-C based filter according to claim 17, wherein the 1th sub-circuitry comprises an OTRA having an negative input, an positive input and an output, and the output is connected to the negative input through a capacitor, and the positive input is grounded, and the negative input is connected to the voltage output terminal through a resistor.
 20. The ASM for designing OTRA-C based filter according to claim 1, wherein the OTRA-C based filter comprises n OTRAs and n capacitors to serve as an odd nth order voltage-mode OTRA-C based universal filter.
 21. The ASM for designing OTRA-C based filter according to claim 20, wherein the OTRA-C based filter comprises n sub-circuitries and n is an odd number, and wherein each of the kth sub-circuitries, k=2, 4, . . . , n−3, comprises an OTRA having a negative input, a positive input and an output, and the output is connected to the negative input through a capacitor, and the negative input is connected to a voltage output terminal through a resistor, and the positive input is connected to an output of the OTRA of the k−1th sub-circuitry through a resistor.
 22. The ASM for designing OTRA-C based filter according to claim 21, wherein each of the jth sub-circuitries, j=3, 5, . . . , n−2, comprises an OTRA having a negative input, a positive input and an output, and the output is connected to the negative input through a capacitor, and the negative input is connected to the voltage output terminal through a resistor, and the positive input is simultaneous connected to the output of OTRA of the j−1th sub-circuitry through a resistor and connected to a voltage input terminal through a resistor.
 23. The ASM for designing OTRA-C based filter according to claim 22 wherein the n−1th sub-circuitry comprises an OTRA having a negative input, a positive input and an output, and the output is connected to the voltage output terminal through a resistor, and the negative input is connected to an output of the OTRA of the nth sub-circuitry through a capacitor, and the positive input is connected to the output of the OTRA of the n−2th sub-circuitry through a resistor.
 24. The ASM for designing OTRA-C based filter according to claim 23, wherein the nth sub-circuitry comprises an OTRA having a negative input, a positive input and an output, and the output is connected to the negative input through a resistor, and the positive input is connected to the voltage input terminal through a resistor and a capacitor connected in parallel, and the negative input is connected to the voltage input terminal through a resistor.
 25. The ASM for designing OTRA-C based filter according to claim 22, wherein the 1th sub-circuitry comprises an OTRA having a negative input, a positive input and an output, and the output is connected to the negative input through a capacitor, and the positive input is connected to the voltage input terminal through a resistor, and the negative input is connected to the voltage output terminal through a resistor.
 26. The ASM for designing OTRA-C based filter according to claim 1, wherein the OTRA-C based filter comprises n OTRAs and n+1 capacitors to serve as an even nth order voltage-mode OTRA-C based universal filter.
 27. The ASM for designing OTRA-C based filter according to claim 26, wherein the OTRA-C based filter comprises n sub-circuitries and n is an even number, and wherein each of the kth sub-circuitries, k=2, 4, . . . , n−2, comprises an OTRA having a negative input, a positive input and an output, and the output is connected to the negative input through a capacitor, and the negative input is connected to a voltage output terminal through a resistance, and the positive input is connected to an output of the OTRA of the k−1th sub-circuitry through a resistor.
 28. The ASM for designing OTRA-C based filter according to claim 27 wherein each of the jth sub-circuitries, j=3, 5, . . . , n−3, comprises an OTRA having a negative input, a positive input and an output, and the output is connected to the negative input through a capacitor, and the negative input is connected to the voltage output terminal through a resistor, and the positive input is simultaneously connected to a voltage input terminal through a resistor and connected to the output of the OTRA of the j−1th sub-circuitry through a resistor.
 29. The ASM for designing OTRA-C based filter according to claim 28, wherein the n−1th sub-circuitry comprises an OTRA having a negative input, a positive input and an output, and the output is connected to the negative input through a resistor, and the negative input is connected to an output of the OTRA of the nth sub-circuitry through a capacitor, and the positive input is simultaneously connected to the output of the OTRA of the n−2th sub-circuitry through a resistor and connected to the voltage input terminal through a resistor.
 30. The ASM for designing OTRA-C based filter according to claim 29, wherein the nth sub-circuitry comprises an OTRA having a negative input, a positive input and an output, and the output is connected to the negative input through a resistor, and the positive input is connected to the voltage output terminal through a resistor and a capacitor connected in parallel, and the negative input is connected to the voltage input terminal through a capacitor.
 31. The ASM for designing OTRA-C based filter according to claim 28, wherein the 1th sub-circuitry comprises an OTRA having a negative input, a positive input and an output, and the output is connected to the negative input through a capacitor, and the positive input is connected to the voltage input terminal through a resistor, and the negative input is connected to the voltage output terminal through a resistor.
 32. The ASM for designing OTRA-C based filter according to claim 1, wherein the OTRA-C based filter comprises n+1 OTRAs and n capacitors to serve as an even nth order voltage-mode OTRA-C based universal filter.
 33. The ASM for designing OTRA-C based filter according to claim 32, wherein the OTRA-C based filter comprises n+1 sub-circuitries and n is an even number, and wherein each of the kth sub-circuitries, k=2, 4, . . . , n−2, comprises an OTRA having a negative input, a positive input and an output, and the output is connected to the negative input through a capacitor, and the negative input is connected to a voltage output terminal through a resistor, and the positive input is connected to an output of the OTRA of the k−1th sub-circuitry through a resistor.
 34. The ASM for designing OTRA-C based filter according to claim 33, wherein each of the jth sub-circuitries, j=3, 5, . . . , n−1, comprises an OTRA having a negative input, a positive input and an output, and the output is connected to the negative input through a capacitor, and the negative input is connected to the voltage output terminal through a resistor, and the positive input is simultaneously connected to a voltage input terminal through a resistor and connected to the output of the OTRA of the j−1th sub-circuitry through a resistor.
 35. The ASM for designing OTRA-C based filter according to claim 34 wherein the nth sub-circuitry comprises an OTRA having a negative input, a positive input and an output, and the output is connected to the voltage output terminal, and the negative input is simultaneously connected to an output of the OTRA of the n+1th sub-circuitry through a capacitor and connected to the voltage output terminal, and the positive input is connected to the output of the OTRA of the n−1th sub-circuitry through a resistor.
 36. The ASM for designing OTRA-C based filter according to claim 35, wherein the n+1th sub-circuitry comprises an OTRA having a negative input, a positive input and an output, and the output is connected to the negative input through a resistor, and the positive input is connected to the voltage output terminal through a resistor, and the negative input is connected to the voltage input terminal through a resistor.
 37. The ASM for designing OTRA-C based filter according to claim 34, wherein the 1th sub-circuitry comprises an OTRA having a negative input, a positive input and an output, and the output is connected to the negative input through a capacitor, and the positive input is connected to the voltage input terminal through a resistor, and the negative input is connected to the voltage output terminal through a resistor. 